Tuesday, November 22, 2005

How Many Qubits Can Dance on the Head of a Pin?

[Third installment in examining the meaning of scaling a quantum computer. First is here, second one is here. Continued in installment four, here]

I have the cart slightly before the horse in my breadbox posting. In that posting, we were talking about a multi-node quantum computer and its relationship to scalability. But before getting to my quantum multicomputer, we should look at the scalability of a single, large, monolithic machine.

Again, let's consider VLSI-based qubits. In particular, let's look at the superconducting Josephson-junction flux qubit from Dr. Semba's group at NTT (one good paper on it is this one). Their qubit is a loop about 10 microns square. This area is determined by physics, not limited by VLSI feature size; the size of the loop determines the size of the flux quantum, which in turn determines control frequencies, gate speed, and whatnot. (The phase qubit from NIST is more like 100 microns on a side; it's big enough to see!) Semba-san's group is working hard on connecting qubits via an LC oscillator. The paper cited above shows that one qubit couples to the bus; the next step might be two qubits.

So, once they've achieved that, is it good enough? Do they then meet DiVincenzo's criterion for a scalable set of qubits? Let's see. As an engineer, I don't care if the technology scales indefinitely, I care if it scales through regions that solve interesting problems. In this case, we're looking for up to a quarter of a million physical qubits. Can we fit them on a chip? At first glance, it would seem so. Even a small 10mm square chip would fit a million 10-micron square structures. But that ignores I/O pads. Equally important, a glance at the micrograph in the paper above shows that the capacitor is huge compared to the qubit (but you only need one of those per bus that connects a modest-sized group of qubits, and it may be possible to build the capacitor in some more space-efficient manner, or maybe even put it off-chip?). Still more important, these qubits are magnetic, not charge; place them too close together, and they'll interfere. I have no idea what the spacing is (though I assume Semba-san and the others working on this type of qubit have at least thought about this, and may even have published some numbers in a paper I haven't read or don't recall). Control is achieved with a microwave line run past the qubit, so obviously you can't run that too close to other qubits. All of this is a long-winded way of saying there's a lot of physics to be done even before the mundane engineering of floor-planning. We talked a little in the last installment about the need for I/O pads and control lines into/out of the dil fridge. That applies directly to the chip, as well; now we need roughly a pin per qubit, unless a lot more of the signal generators and whatnot can be built directly into our device. Without some pretty major advances in integration, I'll be surprised if you can get more than a thousand qubits into a chip (whether they're charge, spin, flux, what have you). So does that mean we're dead? We can't reach a quarter of a million qubits?

The basic idea of the quantum multicomputer is that we can connect multiple nodes together. We need to create an entangled state that crosses node boundaries, so we need quantum I/O. So, you need the ability to entangle your stationary qubit with something that moves - preferably a photon, though an electron isn't out of the question; a strong laser probe beam may work, too. Then you need a way to get the information out of that photon back into another qubit at the destination node. This is going to be hard, but the alternative is a quantum computer that doesn't extend outside the confines of a single chip. This idea of distributed quantum computing goes back a decade, and there have been some good experiments in this area; I'll post some links references another time.

Bottom line: for the foreseeable future, scalability requires I/O - classical for sure, and maybe quantum. More than a matter of die space for the qubits themselves, I/O pads and lines and space for them on-chip, plus physical interference effects, will drive how many qubits you can fit on a chip. If that number doesn't scale up to the point where it is not the limiting factor in the size of system you can build, then you have to have quantum I/O (some way to entangle on-chip qubits with qubits in another device or another technology).

[Update: Semba-san tells me that the strength of the interaction could be a problem if the qubits are only a micron apart, but at 10um spacing, the interaction drops to order of kHz, low enough not to worry about much.]

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